Biologically Inspired Predictive Gating Signed-Dyadic Coding for Mandarin Keyword Spotting

Introduction

Continuous keyword spotting processes an acoustic stream one frame at a time under tight energy and latency budgets. Adjacent log-mel frames are temporally correlated, but a dense input interface still transfers every frame and repeatedly triggers memory access and downstream computation. The input interface therefore adds work even when hidden activity is sparse. Biological predictive processing, efficient coding, and sensory adaptation describe related mechanisms in which a system maintains an internal estimate, attenuates predictable input, and responds selectively to deviations [1, 2, 7, 8, 16, 21]. We translate this mechanism into a local-state encoder that preserves predictable content and transmits significant mismatches.

Existing event encoders expose different trade-offs. Rate coding represents amplitude through repeated events over a time window, and TTFS coding represents it through spike latency [13, 17]. Delta-style encoding uses changes from a reference state, but applying the same operation to already thresholded hidden spikes can create events for both rising and falling transitions. The placement of an event code therefore matters as much as the code itself.

We propose Predictive Gating Signed-Dyadic Coding (PG), a trainable lossy event code for the acoustic input. PG maintains a local prediction for each channel, computes the residual from the current frame, and emits an event only when the residual crosses a learned threshold. Each event carries a sign and a magnitude selected from a finite dyadic alphabet. The receiving datapath reconstructs each update with fixed-point comparisons, shifts, and additions, yielding a multiplier-free interface.

We evaluate Mandarin keyword spotting with three deployment schemes. DIRECT encodes every input frame, INPUT-PG applies PG only at the acoustic input, and ALL-PG applies PG at the input and hidden boundaries. On 720 test clips, INPUT-PG reaches 90.00% accuracy while reducing mean SRAM reads by 33.87% and inference cycles by 32.77%. A routed evaluation on one fixed clip reports a 39.49% reduction in incremental inference energy, excluding weight loading. Software workload is evaluated over 720 test clips, whereas routed energy is evaluated on one fixed clip.

The resulting study identifies selective input prediction as the useful deployment point for this task. It connects temporal redundancy in acoustic frames with measurable reductions in memory traffic and execution work, and provides a hardware interface for low-power continuous speech processing and event-based sensory systems.

Our contributions are the following.

1. Predictive Gating Signed-Dyadic Coding (PG), a trainable lossy event code that maintains a local prediction, suppresses predictable input, and represents threshold-crossing residuals with a finite signed-dyadic alphabet for fixed-point reconstruction;

2. A selective placement principle for predictive event coding, evaluated through DIRECT, INPUT-PG, and ALL-PG across a feedforward Deep-SNN and a causal LIF-TCN. The comparison shows why prediction is useful where temporal redundancy remains, whereas coding an already thresholded hidden stream can add workload.

3. A 720-clip integer evaluation that jointly measures task accuracy, input activity, SRAM reads, and inference cycles. INPUT-PG reaches 90.00% accuracy and reduces mean SRAM reads and inference cycles by 33.87% and 32.77%.

4. A routed Sky130HD evaluation that measures a 39.49% reduction in incremental inference energy for one fixed hardware clip, excluding weight loading. Software accuracy and workload are evaluated separately over 720 test clips.

Related Work

Biological foundations

Biological sensory systems adapt their responses to the temporal statistics of stimulation. Predictive processing proposes that neural circuits maintain an internal estimate of incoming signals and emphasize deviations from that estimate [8, 16]. Sensory adaptation produces a weaker response to persistent stimulation and restores responsiveness when the stimulus changes [7, 21]. Efficient coding provides a complementary account in which limited neural resources are preferentially allocated to stimulus components that are less predictable from their statistics [1, 2, 11].

Together, these mechanisms describe a biological response pattern in which an internal estimate is maintained, predictable stimulation is attenuated, and deviations receive stronger responses. This pattern provides the biological principle for PG.

Hardware-efficient event coding

SNN accelerators exploit sparse hidden spikes, but a dense acoustic interface can still repeatedly move frames and trigger input-side work. The hardware benefit of an event code therefore depends on its payload, state, routing, and decoder cost, in addition to event count. We report communication activity, digital workload, and routed physical energy as separate measures.

Existing encoders expose different trade-offs. DeltaKWS suppresses changes in acoustic features and recurrent states to avoid redundant updates [10]. Rate coding represents amplitude through repeated events over a time window, whereas TTFS represents it by spike latency. Our RATE-T8 and TTFS-T8 baselines replay quantized amplitudes at the input while retaining the frame loop. Sigma–Delta modulation shapes quantization error through an integrator and feedback loop [19]. PG keeps an explicit local prediction and sends an addressable signed update from a finite dyadic alphabet once the residual crosses a threshold.

PG is applied at the acoustic input, where adjacent log mel frames retain temporal redundancy before entering the SNN. Hidden LIF boundaries already expose thresholded binary events, so PG incurs packet, state, and decoder costs on an already sparse stream. We compare input and hidden placement and count event, SRAM, cycle, and decoder costs for each.

Method

We define the method through four linked components. They are a biological computational abstraction, a selective event interface, a hardware datapath, and a measurement protocol. Each component is evaluated under a common deployment contract for its event, memory, and energy consequences.

Biologically inspired abstraction of prediction errors

We abstract these mechanisms as a local-state predictor that retains predictable sensory content and emits a sparse directed update for an unexpected change. The following equations define this abstraction in accelerator-level quantities.

For each encoded boundary, time step $t$, and address $a$, let $x_{t,a}$ be the signed input and $p_{t,a}$ its synchronized local prediction state, initialized by $p_{0,a}=0$. The trainable parameters are constrained as $s=\operatorname{softplus}(\theta_s)+10^{-6}$, $\tau=\operatorname{sigmoid}(\theta_\tau)$, and $\alpha=\operatorname{sigmoid}(\theta_\alpha)$. A leaky prediction and residual are

Here $s>0$ is the learned scale, $\tau\in(0,1)$ is the normalized threshold, and $\alpha\in(0,1)$ is the predictor coefficient; each is frozen as a fixed point constant in the RTL experiment. With $\mathcal{K}=\{0,1,\ldots,K_{\max}\}$ denoting the available exponent slots, the normalized magnitude and hard gate are

For every active address, exponent selection and decoded residual are

When $g_{t,a}=1$, the transmitted packet is $e_{t,a}=(a,\operatorname{sgn}(r_{t,a}),k_{t,a})$; otherwise no packet is emitted for that address. Let $m_t\in\{0,1\}$ indicate a valid frame that is not padding. The reconstructed output and state update are

For a valid address whose normalized residual is below the threshold, $q_{t,a}=0$ and the state advances through the shared predictor. A padding frame emits zero and holds the previous state. The forward path suppresses subthreshold residuals and advances the state through the shared predictor. During training, the gate uses $g^{\mathrm{soft}}_{t,a}=\operatorname{sigmoid}(12(u_{t,a}-\tau))$ and the straight-through value $g^{\mathrm{ST}}_{t,a}=g^{\mathrm{soft}}_{t,a}+\operatorname{stopgrad}(g_{t,a}-g^{\mathrm{soft}}_{t,a})$. Exponent selection uses the analogous straight-through construction with $r_{t,a}/s$ as its backward surrogate [14]. The forward computation uses the hard event representation defined above.

Signed-dyadic payload and hardware compatibility

The sign preserves the direction of a change, while the finite exponent set preserves a coarse magnitude hierarchy. Since $2^{-k}$ is a shift, decoding can be implemented by sign extension, shift selection, and add/subtract. The resulting datapath uses fixed-point operations instead of a general multiplier, floating-point exponentiation, or a large lookup table. The number of exponent slots, scale, threshold, and predictor leak are explicit knobs for the accuracy–activity–energy frontier. These parameters implement selective responses with multiple magnitudes in the hardware datapath.

For INPUT-PG trained from scratch, the learned scale, normalized threshold, and predictor coefficient average (0.2118, 0.2306, 0.8917) for Deep-SNN and (0.2186, 0.2321, 0.8949) for LIF-TCN across the three seeds. The routed Deep-SNN assets freeze these quantities as scale_q15 = 6863, threshold_q15 = 7472, and alpha_q16 = 58629. The same constants are used during integer inference.

Selective placement

We compare three placement schemes. DIRECT encodes every input frame densely and uses ordinary LIF spikes at the hidden boundaries. INPUT-PG applies PG only at the acoustic input. ALL-PG applies PG at both the input and hidden boundaries.

INPUT-PG is the primary design because the input is both temporally correlated and not yet explicitly sparse. Hidden LIF spikes have already undergone a thresholding operation, so encoding their transitions can add traffic. A layer $\ell$ is therefore a candidate for PG only if the expected savings exceed the packet, state, and decoder cost. We express this condition as

Equation (5) gives the placement criterion used to interpret the three variants. Figure 2 compares the placements and illustrates their different boundary semantics.

Accelerator architecture and hardware verification

Event packet and decoder datapath

Each PG event contains an address, a valid bit, a sign, and an exponent. The decoder sign extends the payload, shifts it by the selected exponent, and accumulates it into a predictor register. These operations implement the prediction update with integer arithmetic. The routed accounting includes event routing, state registers, comparator activity, clocking, SRAM reads, and decoder activity.

Routed implementation and energy accounting

We map the four-layer Deep-SNN with the Sky130HD library at the typical corner, 25 °C, 1.8 V, and a nominal 10 MHz clock. From the routed ODB and SPEF files, we generate functional gate-level FST activity without propagation delays, convert all nets to hierarchical SAIF, and annotate OpenROAD power. The reported runs annotate 100% of nets; internal driver-pin coverage is at least 90.87%, and SPEF coverage is at least 96.87%.

Resident energy assumes that weights are already in SRAM. Transported energy adds the fixed 220,948-byte weight load. The energy boundary excludes the analog front end, ADC, log mel extraction, package, off-chip memory, and system I/O. Let $n_{\mathrm{start},v}$ and $n_{\mathrm{stop},v}$ delimit the inference phase of variant $v$ after parameter loading. Let $r_{v,p}[n]$ denote the read enable of logical SRAM port $p$. The measured work quantities are

In the RTL, the read counter increments once in each state that reads a weight, a hidden bias, or an output bias. With average dynamic powers $P_{\mathrm{infer},v}$, $P_{\mathrm{load},v}$, and $P_{\mathrm{idle},v}$ measured over their respective windows,

Subtracting the idle baseline isolates incremental dynamic work, while active energy retains the physical activity window. The routed table uses seed 17 and clip 3826 with 232 valid frames. All five variants use the same SRAM organization, weight image size, variant-specific weights, and PVT conditions.

RTL consistency and implementation status

The integer software evaluator matches RTL simulations on 8-frame and 64-frame prefixes and on the complete 232-frame test clip. The checks compare logits, predictions, event counts, SRAM reads, and execution cycles. Software evaluation covers all 720 test clips. Routed measurements use one frozen clip, while integer accuracy and workload means use the full test set. The routed run is reported as a prototype evaluation with the measured timing and DRC status.

Experimental protocol and measurement methodology

Task and data

The corpus contains 4,545 Mandarin utterance clips from 101 speakers and five keyword classes. The training, validation, and test partitions contain 3,150, 675, and 720 clips, respectively, with no speaker overlap between partitions. We resample audio from 48 kHz to 16 kHz and represent it with 40-channel log mel features over at most 560 frames. Normalization uses training-set statistics, and padding frames are excluded from event and activity counts. Each test clip contains an average of 248.311 valid frames, or 9,932.444 dense feature values.

Networks and fair training

The Deep-SNN has $40 \to256 \to256 \to128 \to5$ linear layers with three streaming LIF hidden layers, $\beta= 0.9$, threshold 1.0, and subtractive reset (109,841 parameters). The LIF-TCN has four causal residual Conv1d/LIF blocks with dilations 1, 2, 4, and 8, masked temporal pooling, and a five-output classifier (99,284 parameters). DIRECT, INPUT-PG, and ALL-PG are each trained from scratch for 50 epochs with seeds 7, 17, and 27. Training uses batch size 128, learning rate $10^{-3}$, weight decay $10^{-4}$, six exponent slots, and cross-entropy loss. Validation accuracy selects checkpoints, and the test set is not used for epoch selection. Training runs on the device identified as cuda:0. For each architecture and seed, the corresponding variants share the same initialization fingerprint before PG is applied.

We additionally train RATE-T8 and TTFS-T8 on the same Deep-SNN to compare input coding at the scale of the main network. The data partitions are unchanged and contain no speaker overlap. Training uses 50 epochs, batch size 128, AdamW with learning rate 0.001, weight decay 0.0001, and seeds 7, 17, and 27. Checkpoints are selected by validation accuracy. Each new run shares the corresponding DIRECT initialization fingerprint before PG is applied. DIRECT checkpoints serve as the controls. Both encoders operate only at the input; the architecture, acoustic-frame loop, and hidden LIF dynamics remain unchanged.

RATE-T8 replaces a signed feature with a quantized amplitude at magnitude levels 0–8 and counts that level as the number of input events. TTFS-T8 uses magnitude levels 0–7 and counts one event for each nonzero level. In software, both replay signed quantized amplitudes. In RTL, RATE-T8 replays signed unit contributions through the input synapses, whereas TTFS-T8 sends one signed decoded amplitude per active channel. Both encoders retain the original frame loop and operate at the input boundary.

Integer inference protocol

The integer evaluator uses the frozen seed-17 Deep-SNN weights on all 720 test clips from the same split. The partitions have no speaker overlap. Features and PG state use 15 fractional bits, weights use 9 fractional bits, and membrane accumulation uses 24 fractional bits with a leak coefficient represented with 16 fractional bits. PG uses six dyadic exponent slots and compares full integer products in the threshold test. Prediction, residual, and accumulator operations retain their specified signed widths. Input activity counts dense feature values for DIRECT and emitted input events for PG. The evaluator counts SRAM reads for weights and biases and computes inference cycles from the event schedule, excluding parameter loading. Workloads are reported as arithmetic means per clip.

Activity and statistical conventions

For variant $v$, seed $r$, and clip $c$, let $T_c$ be the number of valid frames, $D = 40$ the input dimension, $\mathcal{B}^{\mathrm{PG}}_v$ the set of boundaries encoded by PG, and $\mathcal{B}^{\mathrm{LIF}}$ the set of unencoded hidden LIF boundaries. With $g^{(b)}_{v,r,c,t,a}$ the PG valid bit and $s^{(\ell)}_{v,r,c,t,j} \in\{0,1\}$ the hidden spike, the complete communication proxy for one clip is

where $\mathcal{V}_{c,b}$ contains only valid time–address pairs, excluding padding. Under this definition, DIRECT counts dense input values and ordinary hidden spikes, INPUT-PG counts input PG events and ordinary hidden spikes, and ALL-PG counts PG events at every encoded boundary. This quantity is an activity proxy. For $n$ seeds and $N$ test clips, its reported mean and relative change are

Input-boundary activity uses the same equations after restricting Eq. (8) to the input term. A negative $\Delta A_v$ denotes a reduction, whose positive magnitude is $R_{A,v}=-\Delta A_v$.

For RATE-T8 and TTFS-T8, the complete proxy is the number of encoded input events plus positive spikes from all three hidden LIF layers. This replaces the dense-input term in Eq. (8) and adds no hidden PG boundary. All counts exclude padding and use the same clip and seed averaging in Eq. (9).

Test accuracy for seed $r$ is the percentage of correctly classified test clips. Its mean and sample standard deviation across seeds are

For a paired comparison with DIRECT, $d_r=a_{v,r}-a_{\mathrm{DIRECT},r}$ in percentage points. With $\overline{d}=n^{-1}\sum_r d_r$ and $s_d^2=(n-1)^{-1}\sum_r(d_r-\overline{d})^2$, the reported two-sided 95% interval is

With $n=3$, these intervals describe uncertainty across seeds. For any workload or routed metric $m\in\{C,N_{\mathrm{read}},P,E,\mathrm{area}\}$, the tables use the same baseline convention,

Routed measurements use one frozen clip; integer workload means use all 720 test clips.

Evaluation tracks

Table 1 summarizes the evaluation tracks. From-scratch training measures accuracy and communication activity across two architectures and three seeds. Integer inference measures accuracy and mean workload with frozen Deep-SNN weights on all 720 test clips. The routed experiment measures energy for five implementations on one fixed clip. The movable-SRAM study evaluates an additional accuracy–energy frontier on a separate microarchitecture.

Track	Question	Population	Primary outputs	Scope
E1 from scratch, 50 epochs	Task performance	2 architectures, 3 seeds, 720 clips	accuracy, activity proxy	software; rate/TTFS on Deep-SNN
E5 routed	Energy cost of work	Deep-SNN, seed 17, clip 3826	cycles, reads, power, energy	one fixed clip, after routing
Integer inference	Accuracy and workload	Deep-SNN, seed 17, 720 clips	accuracy, cycles, reads	integer software; frozen weights
Small movable	Separate frontier	40 → 64 → 5, seed 17	Q9 accuracy, routed energy	separate microarchitecture

Experimental results

Accuracy and activity across architectures

Across both architectures, INPUT-PG keeps the observed accuracy close to DIRECT while reducing communication activity (Table 2). Its mean accuracy is 88.47% for Deep-SNN and 88.10% for LIF-TCN, compared with 88.84% and 88.75% for DIRECT. Input events fall from 9,932.444 dense values per clip to 2,806.5 and 2,684.8, giving reductions of 71.74% and 72.97%, respectively. Complete communication activity falls by 20.07% and 19.74%. Across the three seeds, the paired intervals are compatible with the DIRECT values, while input and complete activity are consistently lower. Figure 3(a-Figure 3b) shows the accuracy and activity comparison.

Architecture	Variant	Accuracy (%)	Input/coded events	Hidden spikes	Complete proxy	Δ proxy
Deep-SNN	DIRECT	88.84 ± 1.55	0.0	19,344.3	29,276.8	0.00%
	INPUT-PG (ours)	88.47 ± 3.70	2,806.5	20,595.0	23,401.5	−20.07%
	ALL-PG (ours)	88.66 ± 0.45	27,788.7	diagnostic	27,788.7	−5.08%
	RATE-T8	88.61 ± 1.77	12,867.6	19,290.2	32,157.8	+9.84%
	TTFS-T8	86.94 ± 1.25	7,610.9	19,502.7	27,113.6	−7.39%
LIF-TCN	DIRECT	88.75 ± 2.57	0.0	26,283.6	36,216.1	0.00%
	INPUT-PG (ours)	88.10 ± 0.21	2,684.8	26,381.5	29,066.3	−19.74%
	ALL-PG (ours)	86.85 ± 1.45	30,289.9	diagnostic	30,289.9	−16.36%

On Deep-SNN, RATE-T8 and TTFS-T8 reach 88.61% ± 1.77% and 86.94% ± 1.25%, respectively. Their paired mean differences from DIRECT are −0.23 pp (95% interval [−2.34, 1.88]) and −1.90 pp ([−3.29, −0.50]) (Table 3). RATE-T8 increases the complete proxy by 9.84%, whereas TTFS-T8 reduces it by 7.39% with a consistent accuracy loss across the three seeds. INPUT-PG has the lowest complete proxy among the five Deep-SNN variants. These comparisons use the finite input implementations defined in the protocol.

Architecture	Comparison	Mean [95% CI]
Deep-SNN	INPUT-PG (ours)–DIRECT	−0.37 [−5.73, 4.99]
Deep-SNN	ALL-PG (ours)–DIRECT	−0.19 [−3.99, 3.62]
Deep-SNN	RATE-T8–DIRECT	−0.23 [−2.34, 1.88]
Deep-SNN	TTFS-T8–DIRECT	−1.90 [−3.29, −0.50]
LIF-TCN	INPUT-PG (ours)–DIRECT	−0.65 [−6.73, 5.43]
LIF-TCN	ALL-PG (ours)–DIRECT	−1.90 [−8.27, 4.48]

The boundary counts explain why the benefit is concentrated at the input. In the Deep-SNN, the input boundary emits 2,917.9 events per clip, whereas the three hidden boundaries emit 10,659.0, 10,735.7, and 3,476.2 events. In the LIF-TCN, the four block boundaries emit 5,432.8, 5,059.0, 6,016.2, and 10,808.8 events. These hidden boundaries already carry binary, sparse LIF activity, so encoding their transitions can add packet traffic instead of removing redundancy. This pattern accounts for the higher complete proxy of ALL-PG and supports placing PG at the acoustic input. Figure 3(c-Figure 3d) shows the counts.

Routed energy

For one fixed clip after Sky130HD routing, INPUT-PG reduces inference cycles by 33.76% and SRAM reads by 34.70% (Table 4). Its instantaneous inference dynamic power is 1.23% higher than DIRECT, but resident and transported energy after idle subtraction decrease by 39.49% and 39.44%, respectively. ALL-PG also consumes less energy than DIRECT, although its reduction is smaller than that of INPUT-PG. The energy saving follows the shorter execution window and lower memory traffic, which determine the integrated energy. Figure 4(A-E) shows the estimates.

Table 4. Deep-SNN results after routing for seed 17, frozen clip 3826 (232 frames). Sky130HD TT, 25 °C, 1.8 V, nominal 10 MHz. Energy is incremental energy after subtracting the idle baseline; Resident excludes weight load and Transported includes it. RATE-T8 and TTFS-T8 use the implementations applied only at the input, as defined in the experimental protocol.

Variant	Cycles	SRAM reads	Inference dyn. (mW)	Resident ($\mu$J)	Transported ($\mu$J)	Area ($\mathrm{mm}^2$)
DIRECT	11,792,327	5,737,243	273.645	33,252.992	33,290.587	43.785
INPUT-PG (ours)	7,810,745	3,746,452	277.010	20,122.617	20,159.901	44.222
ALL-PG (ours)	9,158,879	4,420,519	278.367	24,943.967	24,979.233	44.369
RATE-T8	16,155,227	7,918,693	269.362	44,365.536	44,400.672	43.638
TTFS-T8	10,639,233	5,160,696	270.449	28,369.628	28,405.549	43.704

INPUT-PG adds about 1.00% area and ALL-PG adds 1.33% relative to DIRECT. Every variant transports the same 220,948 byte weight image, so the load phase changes little; the difference arises during inference. This separates the energy benefit from a weight-loading effect.

For the same fixed clip, RATE-T8 increases cycles and resident energy by 37.00% and 33.42% relative to DIRECT, whereas TTFS-T8 reduces them by 9.78% and 14.69%. INPUT-PG has the lowest resident incremental energy among the five implementations in this frozen physical experiment. Integer accuracy is reported in Tables 2 and 6.

Movable-SRAM trade-off

The movable-SRAM study uses a separate $40 \to64 \to5$ architecture and reports its own accuracy–energy frontier. Previous-K6 PG uses the fewest cycles and the lowest energy in this architecture, but its 79.72% accuracy is 3.61 percentage points below DIRECT.

Table 5. Movable-SRAM experiment with a small network. Q9 accuracy uses 720 test clips; cycles and energy use one frozen clip in the movable-SRAM architecture.

Variant	Q9 acc. (%)	Cycles	Resident ($\mu$J)	Transported ($\mu$J)
DIRECT	83.33	1,374,251	216.633	216.679
RATE-T8	81.53	2,443,449	337.234	337.282
TTFS-T8	82.92	1,102,571	179.086	179.131
Previous-K6 PG (ours)	79.72	703,803	83.651	83.692

Integer inference accuracy and workload

With the frozen seed-17 weights, integer inference on all 720 test clips yields 90.00% accuracy for INPUT-PG (648 clips) and 89.58% for both DIRECT and ALL-PG (645 clips each) (Table 6). Relative to DIRECT, INPUT-PG reduces mean input activity by 71.67%, mean SRAM reads by 33.87%, and mean inference cycles by 32.77%. Thus, in this software evaluation, input prediction preserves the observed task accuracy while lowering the measured workload.

Table 6. Integer software inference on 720 test clips with frozen Deep-SNN weights from seed 17. Workload columns report means per clip and exclude parameter loading. Input activity counts dense values for DIRECT and emitted input events for PG.

Method	Accuracy (%)	Input activity/clip	SRAM reads/clip	Inference cycles/clip
DIRECT	89.58	9,932.44	5,054,116.01	10,448,419.24
INPUT-PG (ours)	90.00	2,813.53	3,342,360.28	7,024,907.79
ALL-PG (ours)	89.58	2,932.49	5,016,142.84	10,372,472.91

The workload advantage depends on placement. ALL-PG matches the observed DIRECT accuracy but requires substantially more SRAM reads and inference cycles than INPUT-PG. The result supports applying prediction at the input instead of extending it to every hidden boundary. Figure 4(F) shows the integer accuracy results.

Discussion

Placement effects

The three evidence tracks point to the same placement rule. Across the two architectures, INPUT-PG reduces input activity by 71.74–72.97% and the complete communication proxy by 19.74–20.07%. The paired intervals are compatible with DIRECT across the three seeds, while activity reductions are consistent across architectures. With frozen integer weights, INPUT-PG reaches 90.00% versus 89.58% for DIRECT and reduces SRAM reads and cycles by 33.87% and 32.77%. In the routed run, the shorter execution window offsets the 1.23% increase in instantaneous dynamic power. ALL-PG requires more work than INPUT-PG in both software evaluations. Together, the results support selective prediction at the input boundary.

Workload and energy

Event counts and physical energy measure different quantities. A PG event carries an address, sign, exponent, and control information, so comparator, predictor, decoder, clock, SRAM, and routing activity all contribute to the hardware work. Instantaneous power depends on packet, predictor, decoder, clock, SRAM, and routing activity, while incremental energy also depends on execution duration. Equation (7) uses a common routed implementation, a defined phase duration, and an idle reference to calculate incremental energy. Software event counts diagnose workload reduction, whereas routed power and energy quantify the corresponding hardware cost.

Conclusion

We introduced Predictive Gating Signed-Dyadic Coding (PG), a selective input event interface that maintains a local prediction and transmits threshold-crossing signed-dyadic residuals. On the integer evaluation, INPUT-PG reached 90.00% accuracy, reducing mean SRAM reads by 33.87% and inference cycles by 32.77%. For one routed clip, INPUT-PG reduced incremental inference energy by 39.49%, excluding weight loading. Input-side predictive coding offers a hardware interface for converting temporal redundancy into lower memory and execution cost. This mechanism provides a concrete basis for research on low-power continuous speech interfaces and event-based sensory systems.

Detailed relative changes

Variant	Cycles	SRAM reads	Inference power
INPUT-PG (ours)	−33.76%	−34.70%	+1.23%
ALL-PG (ours)	−22.33%	−22.95%	+1.73%
RATE-T8	+37.00%	+38.02%	-1.57%
TTFS-T8	-9.78%	-10.05%	-1.17%

Architecture	INPUT-PG (ours)–DIRECT	ALL-PG (ours)–DIRECT
Deep-SNN	−0.37	−0.19
LIF-TCN	−0.65	−1.90