SEU Hardened Multi-Context Spintronic FPGA

Abstract

Due to susceptibility to radiation-induced soft errors and resource constraints implementing large and complex designs on field programmable gate arrays (FPGAs) in harsh environments is challenging. Therefore, to mitigate these issues, this paper proposes an innovative approach through the introduction of a single event upset (SEU)-hardened spintronic FPGA architecture that incorporates multi-context capabilities. Leveraging the non-volatile properties of magnetic tunnel junction (MTJ), the proposed design can store two/four distinct configurations internally, eliminating the dependence on external non-volatile memory which significantly boosts the system performance. Additionally, through post-layout simulation, we demonstrate our design immunity to SEU, which enhances its reliability and operational stability in environments susceptible to radiation-induced soft errors. The efficiency of the proposed design was also evaluated using the ROSSETA benchmark, which serves as a representative model for real-world FPGA applications.