qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits

ACM Reference Format: Ziyu Liu, Jingkai Hong, Robert S. Aviles, Sasan Razmkhah, Peter A. Beerel, and Massoud Pedram. 2027. qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits. In 32nd Asia and South Pacific Design Automation Conference (ASPDAC ’27), January 25–28, 2027, Tokyo, Japan. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/3840404.3848378

INTRODUCTION

Rapid single-flux-quantum (RSFQ) circuits provide ultra-low energy dissipation on the order of $2 \times10^{-19}$ J bit$^{-1}$[15] and have demonstrated operating frequencies of 25–50 GHz [2, 5, 26, 31]. These characteristics position RSFQ as a promising post-CMOS technology for high-performance computing, particularly in domains such as quantum system control [17], neuromorphic computing [16], and high-performance computing on a datacenter-scale [8, 15]. However, RSFQ design poses unique challenges because every logic gate is clocked and fanout requires explicit non-clocked splitter gates.

Addressing these design challenges has led to the development of several RSFQ clocking schemes, including the widely used single-phase approach and alternatives such as concurrent-flow [32] and multi-phase clocking [4, 21]. In this work, we focus on single-phase clocking, where interconnect delay—particularly from long gate-to-gate connections—often dominates the clock period, making placement a timing-critical stage of the design flow.

Existing RSFQ placement algorithms fall into two main categories: level-based methods and CMOS-style analytical placers. Level-based methods [7, 9, 12, 20, 32, 33] exploit the logical pipeline structure of RSFQ circuits by mapping each logic level to exactly one physical row. However, these approaches were developed for concurrent-flow clocking, in which timing is enforced locally at each logic stage. As a result, they neither target single-phase clocking nor control the longest gate-to-gate interconnect. Moreover, the one-row-per-level constraint leads to poor area utilization for highly unbalanced levels.

The state-of-the-art single-phase RSFQ placer qPlace [27] adopts a CMOS-style analytical placement algorithm [18] that minimizes the half-perimeter wirelength (HPWL) via smooth approximations of the $L_1$ norm. However, as illustrated in Figure 1a, this approach produces distributions with long tails (red curve), indicating numerous outlier long wires. Although such outliers are tolerable in CMOS, where delay accumulates over many gates (Figure 1b), they are critical in RSFQ’s gate-level pipelined structure (Figure 1c), in which each gate-to-gate connection defines an independent timing path, and a single long wire can limit the achievable clock frequency.

In this paper, we propose qLevelPlace, a level-based RSFQ placement framework that addresses the challenges of placing fully path-balanced (FPB) RSFQ circuits using single-phase clocking. Our approach focuses on performance optimization while considering area utilization and routability under limited routing resources. As illustrated in Figure 1a, our method (blue) yields a tighter and more uniform wire-length distribution with fewer long critical connections, enabling higher frequency. Our main contributions are:

• Two-stage placement that separates logic gate placement from splitter placement, enabling critical gate-to-gate interconnect length (CIL) minimization.

• Flexible level-to-row assignment that allows a logic level to span multiple physical rows, improving area utilization over rigid one-level-to-one-row assignment schemes.

• Timing-aware edge weighting that derives edge weights from normalized gate-to-gate delays to prioritize critical connections, improving circuit frequency while reducing estimated CIL.

In experiments, qLevelPlace improves clock frequency by up to 3.81× (2.65× on average) over qPlace [27]. Sections 2–5 respectively review RSFQ placement, present qLevelPlace, evaluate it, and conclude the paper.

BACKGROUND AND RELATED WORK

RSFQ Logic

RSFQ logic gates operate on quantized magnetic flux, where information is encoded as single flux quantum (SFQ) pulses. Each pulse represents a binary "1", while the absence of a pulse represents a binary "0". From the perspective of physical design, RSFQ circuits exhibit several distinctive characteristics stemming from this pulse-driven nature:

Limited fanout capability: Unlike CMOS, where one gate can drive multiple sinks via a hyper-net, RSFQ gates can drive a single load. When fanout $> 1$, asynchronous splitter gates must be inserted to duplicate the SFQ pulse. Synthesis tools typically limit this fanout to improve performance [3, 11], and our placement framework respects this constraint by assuming a maximum fanout of four per gate.

Path balancing requirements: Under single-phase synchronous clocking, every gate is clocked and all logic paths must be path-balanced. The logic level $l(g)$ of gate $g$ is recursively defined as $l(g)=\max_{f\in\operatorname{fanin}(g)} l(f)+1$, with $l(g)=0$ for primary inputs. FPB netlists ensure all input paths to any gate traverse the same number of logic gates by inserting path-balancing clocked buffers during synthesis.¹ Importantly, the throughput of an FPB circuit is inversely proportional to its clock period, which is set by the critical-path delay of a single logical stage, comprising a driver gate’s clock-to-Q delay, a receiver gate’s setup delay, the interconnect delay between the gates, and up to two splitter delays for a fanout-of-four. This is in sharp contrast to typical CMOS digital circuits in which the critical path passes through 10–30 gates and their associated interconnects. This dramatic difference motivates our novel RSFQ placement algorithm, which prioritizes minimizing outlier long wires that could otherwise limit clock frequency.

Passive Transmission Lines (PTLs): RSFQ interconnects use superconducting striplines with limited routing layers; PTLs require no repeaters, and their propagation delay scales linearly with length at approximately 1 ps per 100 μm, corresponding to a signal velocity of $\sim c/3$ [22]. bulky inductors and limited fabrication scalability yield large gate-to-gate distances, so despite this high propagation speed, interconnect delay often dominates the clock period.

RSFQ Placement Problem Definition

An RSFQ circuit is represented by a directed graph $G=(V,E)$, where $V=V_{\mathrm{logic}}\cup V_{\mathrm{SPL}}\cup V_{\mathrm{PI}}\cup V_{\mathrm{PO}}$, where $V_{\mathrm{logic}}$ is the set of clocked logic gates, $V_{\mathrm{SPL}}$ is the set of splitters, $V_{\mathrm{PI}}$ the set of primary inputs, and $V_{\mathrm{PO}}$ is the set of primary outputs; $E$ is the set of nets.

The placement problem assigns valid coordinates $(x_i,y_i)$ to all gates under non-overlap constraints, and aims to optimize the geometric characteristics that impact critical-path delays.

Related Work

Existing placement approaches for RSFQ fall into two categories: CMOS-style Placement: Placement in CMOS has been extensively studied, with approaches broadly classified into stochastic methods, e.g., simulated annealing (SA) [25], and analytical methods based on continuous optimization [18]. Some RSFQ placers, such as qPlace [27], adapt analytical placement methods [18] that iteratively solve a reweighted quadratic programming problem whose objective function approximates HPWL. More precisely, the objective function for iteration $k$ is formulated as:

where $c_{ij}^{x(k)}$ and $c_{ij}^{y(k)}$ are connection weights iteratively updated by the Bound2Bound (B2B) net model [18] based on the placement of the previous iteration. This iteratively reweighted quadratic formulation approximates $L_1$-norm HPWL [18].

Level-based placement: Other RSFQ works [7, 13, 20, 32] adopt level-based placement methods which organize gates into rows² only according to their logic level. Gates at the same logic level, which correspond to the same clocked logic stage, are physically aligned on the same placement row. These methods employ concurrent-flow or wave-pipelined clocking schemes [7, 13, 20, 32], which maintain data-path and clock-path synchronization using specialized clock distribution circuits.

Our formulation also exploits the levelized structure of RSFQ circuits and solves the placement problem through a structured quadratic optimization framework.

OUR PROPOSED METHOD

We propose a two-stage placement approach for single-phase RSFQ circuits that decouples the optimization of clocked logic gates from that of unclocked splitters. As illustrated in Figure 1c, RSFQ’s gate-level clocking creates short pipeline stages along each timing path, where stages contain only direct gate-to-gate interconnects or splitter-based fanout. The placement of logic gates impacts critical timing paths and can benefit from timing-driven placement (Stage 1), while splitters are unclocked fanout elements that can be optimized independently after logic gate positions are fixed (Stage 2).

Overview of Two-Stage Approach

Recall that all logic gates are organized into discrete levels, with each level $i$ exclusively driving level $i+1$. We exploit this inherently levelized structure by dividing the Stage 1 task of logic gate placement into two coordinated subproblems as shown in Figure 2.

First, Y-axis row assignment determines the physical row for each gate. We model this as a level-guided allocation problem, in which each level is assigned one or more rows that are spaced to avoid vertical overlap between gates. Second, X-axis placement optimizes horizontal locations within each row using a quadratic formulation that strongly penalizes long interconnects [28], followed by a legalization step to remove any remaining horizontal overlaps. This decomposition capitalizes on the levelized nature of RSFQ circuits to reduce optimization complexity while preserving solution quality [30]. It also enables algorithms tailored to each subproblem: the Y-direction assignment can be restricted to a small set of candidate rows per logic level due to the inherently discrete level structure, whereas the X-direction placement retains continuous freedom, allowing efficient gradient-based optimization.

Placement of splitters is handled separately in Stage 2, as illustrated in Figure 2. Splitters are removed in Stage 1 and then reinserted directly above the driving gate in the wiring channel between placed rows, minimizing added interconnect delay while respecting row-capacity constraints. This two-stage approach enables placing splitters close to their driving gates rather than treating them the same as logic gates. This is critical for high-frequency RSFQ operation, where individual wire delays can directly impact performance.

Stage 1(a): Level Folding and Merging

We formulate the assignment of logic gates to physical rows as an integer linear programming (ILP) problem. Each logic gate $i$ belongs to a logic level $l \in\{1,2,\ldots,L_{\max}\}$, and the physical rows are indexed by $r \in\{1,2,\ldots,R_{\max}\}$, each with Y-coordinate $Y(r)$ and capacity $C$. For each logic level $l$, we define an allowed row interval $[r_l^{\min},r_l^{\max}] \subseteq\{1,\ldots,R_{\max}\}$, where $r_l^{\min}$ and $r_l^{\max}$ denote the minimum and maximum row indices that may be assigned to gates in level $l$. Level folding occurs when gates from a single logic level are distributed across multiple rows ($r_l^{\min} \ne r_l^{\max}$), which happens when the total width of gates at level $l$ exceeds the row capacity $C$. In this case, the level is folded into multiple rows with $k_l = \lceil W_l/C \rceil$, and an ILP assigns gates to rows while respecting capacity constraints. Level merging occurs when the row intervals of adjacent levels overlap ($r_l^{\max} \ge r_{l+1}^{\min}$).

The objective of the Y-direction assignment is to minimize the total inter-row interconnect length for each logic level $l$, computed by summing the cost of assigning each gate in level $l$ to a row $r \in[r_l^{\min},r_l^{\max}]$. Assuming a uniform inter-row spacing, the objective reduces to minimizing the sum of row index differences (see Eq. (3)).³

We optimize one logic level at a time and perform several passes, sweeping levels 1 to $L_{\max}$ and reassigning gates within their candidate rows (Algorithm 1). A monolithic global ILP is not required in FPB RSFQ circuits because the levelized structure naturally supports an iterative level-wise approach. This enables a multi-pass ILP that keeps the problem size tractable while still providing strong solution quality in practice. For a given level $l$, the ILP is formulated as follows:

where $N^l$ represents all the nodes in level $l$, $N^l$ represents all the nodes in row $r$ of the placement; $p$ and $q$ denote the fanout gates of gate $i$. The binary variable $x_{i,r} \in\{0,1\}$ indicates whether gate $i$ is assigned to row $r$. Constraint (4) ensures that each gate is assigned to exactly one row. The variable $w_i$ is the width of cell $i$, constraint (5) enforces the row capacity limit. Note that during the first iteration of the forward pass in Algorithm 1, the fanout nodes’ rows have not been assigned yet; an adjacent row $r_l^{\max}+1$ is assumed to hold all the fanout nodes.

The number of candidate rows per logic level, $r_l^{\max}-r_l^{\min}+1$, is determined by the estimated row capacity $C$, which is computed from the target aspect ratio.

Algorithm 1 Level-by-level row assignment with local ILP folding and greedy merging

Require: Netlist $G(V,E)$; cell width $w(\cdot)$; row capacity $C$

Ensure: Row index $\operatorname{row}(i)$ for each gate $i$

1. $\operatorname{row}(i) \gets-1$ for all $i$

2. for $i_t = 1$ to $ITER\_MAX$ do

3. $r_{\mathrm{cur}} \gets0$

4. for $l = 1$ to $L_{\max}$ do

5. $N_l \gets\operatorname{getAllCellsAtLevel}(l)$

6. $W_l \gets\operatorname{getTotalCellWidth}(N_l,w(\cdot))$

7. $k_l \gets\lceil W_l/C \rceil$ ▷ Desired folds

8. if $k_l \ge2$ then

9. $r_l^{\min} \gets r_{\mathrm{cur}} + 1$, $r_l^{\max} \gets r_{\mathrm{cur}} + k_l$

10. $x^\star\gets\operatorname{ILP}(w(\cdot),C,[r_l^{\min},r_l^{\max}],\operatorname{row}(\cdot))$

11. $\operatorname{row}(i) \gets\arg\max_r x^\star_{i,r}$, $\forall i \in N_l$

12. else

13. if $W_{r_{\mathrm{cur}}} + W_l \le C$ then ▷ Merge with current row

14. $\operatorname{row}(i) \gets r_{\mathrm{cur}}$, $\forall i \in N_l$

15. else ▷ Start new row

16. $r_{\mathrm{cur}} \gets r_{\mathrm{cur}} + 1$, $\operatorname{row}(i) \gets r_{\mathrm{cur}}$, $\forall i \in N_l$

17. end if

18. end if

19. end for

20. end for

21. return $\operatorname{row}(\cdot)$

A key challenge is avoiding the creation of a very small "residue" row where capacity constraint $C$ forces an additional sparsely populated row to accommodate the total width $W_{\mathrm{tot}}$ of a level. The residue is computed as $res = W_{\mathrm{tot}} \bmod C$. If this remainder falls below the utilization threshold, $res < \epsilon\cdot C$, we slightly increase the capacity by $C' \gets C + \Delta C$ so that the leftover gates can be absorbed into the preceding rows. We apply this residue check across all levels and iteratively adjust $C$ until no level produces a residue smaller than $\epsilon\cdot C$, thereby improving row utilization and eliminating wasted area from sparsely filled rows.

Stage 1(b): Intra-Row Placement

Initial Placement Generation: With the Y-direction row assignments fixed, an initial intra-row placement is generated as the starting point for subsequent optimization. For each row $r$, the gates in $V_r$ are uniformly distributed in a random order and spaced apart by a distance $s$. This yields an initial placement width

where $w_i$ is the width of gate $i$. The total placement height is described in Section 3.4.

Intra-Row Placement: Once an initial intra-row placement is generated, we optimize horizontal positions within each row using an iterative row-by-row process in Algorithm 2. The algorithm iterates over all rows, starting with the primary inputs and moving to the primary outputs $N_{\mathrm{iter}}$ times. For each row $r$, only its gates are movable, while connected gates in other rows remain fixed as anchors.

Algorithm 2 Intra-Row Placement

Require: Initial placement $P_0$, netlist $G=(V,E)$, iterations $N_{\mathrm{iter}}$, weight $\lambda$

Ensure: Optimized placement $P^\star$

1. $\operatorname{cost}^\star\gets\infty$

2. for $t = 1$ to $N_{\mathrm{iter}}$ do

3. for each row $r \in\mathcal{R}$ with gate set $V_r$ do

4. ▷ Compute timing-driven edge weights.

5. $\overline{D}_r^{(t-1)} \gets\frac{1}{|E_r|}\sum_{(u,v)\in E_r}\widehat{D}_{uv}^{(t-1)}$

6. for each edge $(i,j) \in E_r$ do

7. $\widehat{D}_{ij} \gets t_{c2q,i} + t_{sp} \cdot t_{sp} + t_{setup} + \alpha\cdot\operatorname{HPWL}^{(t-1)}$

8. ▷ $\alpha$: HPWL-to-delay scaling (PTL)

9. $c_{ij} \gets\widehat{D}_{ij}/\overline{D}_r^{(t-1)}$

10. end for

11. ▷ Solve the quadratic objective for row $r$ using CG

12. $\Phi_r(x) = (1-\lambda)\sum_{(i,j)\in E_r} c_{ij}(x_i-x_j)^2 + \lambda\sum_{i\in V_r}(x_i-\bar{x}_i)^2$

13. $x_i^\star\gets\arg\min_{x_i}\Phi_r(x)$, $\forall i \in V_r$

14. $\mathcal{P} \gets\operatorname{LEGALIZE}(V_r,x^\star)$

15. end for

16. $\operatorname{avgHPWL} \gets\operatorname{HPWL}(\mathcal{P})/|E|$

17. $\operatorname{maxIL} \gets\max_{(i,j)\in E}\|\mathcal{P}(i)-\mathcal{P}(j)\|_1$

18. $\operatorname{cost} \gets\operatorname{avgHPWL}+\operatorname{maxIL}$

19. if $\operatorname{cost}<\operatorname{cost}^\star$ then $P^\star\gets\mathcal{P}$, $\operatorname{cost}^\star\gets\operatorname{cost}$

20. end for

21. return $P^\star$

For row $r$, we solve the quadratic placement problem:

where $V_r=\{i\in V:y_i=Y_r\}$, $E_r=\{(i,j)\in E:i\in V_r\lor j\in V_r\}$, $N_i=\{j\in V:(j,i)\in E\lor(i,j)\in E\}$. The first term is a quadratic wirelength penalty that reduces total interconnect length while suppressing long gate-to-gate connections. The edge weight $c_{ij}$ is derived from a timing-based delay estimate between cells $i$ and $j$, computed from the previous placement iteration and normalized by the average path delay, where $t_{c2q,i}$, $t_{setup}$, $n_{sp}$, and $t_{sp}$ denote the clock-to-Q delay of cell $i$, the setup time of cell $j$, the splitter count, and the splitter delay, respectively. The second term anchors each gate toward the midpoint of its neighbors. A larger $\lambda$ increases the influence of this centering term, while a smaller $\lambda$ makes the quadratic wirelength penalty dominant.

We first relax Equation (8) and solve the quadratic placement objective using conjugate gradient descent [18, 30]. This produces continuous gate positions that may contain overlaps and serve as target coordinates for subsequent legalization. We then enforce the non-overlap constraint using a Tetris-style legalization algorithm [14]. Because each optimization pass updates only one row, legalization is performed independently within that row: gates are sorted by their optimal X-coordinates, and placed sequentially from left to right. Each gate is positioned at $\max(x_{\mathrm{optimal}},x_{\mathrm{bar}})$, where $x_{\mathrm{bar}} tracks the right edge of the last placed gate. If the placement exceeds the row boundary, a secondary scan is performed in the opposite direction. This row-by-row optimization keeps all other rows fixed, efficiently reduces overlap while preserving connectivity, and is inspired by the Look-Ahead Legalization (LAL) technique [18, 19].

Stage 2: Splitter Placement

Datapath Splitter Insertion: After logic gates are placed, splitters are inserted to satisfy fanout. Prior level-based RSFQ placers [6, 9, 20, 32, 33] do not specify how data splitters are placed; we introduce a post-placement strategy for inserting splitters.

Given our level-based structure, we adopt a vertical attachment strategy: splitters are placed directly above their driving gates by extending the layout vertically. This design is motivated by two RSFQ properties: Timing: Critical delay is dominated by horizontal gate-to-gate interconnects; the added splitter connection is short and has negligible impact. Routability: Vertical attachment reduces horizontal congestion in inter-level routing channels. This approach is effective because our circuits are designed with shallow fanout trees ($\le4$); however, incorporating more sophisticated splitter-tree optimization remains a promising direction for future work.

Clock Splitter and Routing Space: In the MIT-LL SFQ5ee technology [29], while the full process stack contains nine layers, only two metal layers are available for PTL routing, placing tight constraints on available routing resources. Because of these limited routing resources and the need to accommodate clock splitters inserted between rows, efficient use of vertical spacing becomes critical. To address this, we incorporate a congestion-aware model into the Y-axis spacing between consecutive rows. For each net connecting pins $a$ and $b$, we estimate routing demand using pin midpoint locations and calculate the total number of routing tracks required between consecutive rows. The Y-axis spacing between two given rows is then adjusted as:

where $D_{i,i+1}$ is the number of nets crossing between consecutive rows, $P_w$ is the wire pitch, $h_{\mathrm{splitter}}$ is the height of a clock splitter, and $\alpha$ is an empirically-set expansion factor. Here, $S_{\mathrm{base}}$ provides the baseline separation needed for data splitters and signal routing, while the max term reserves additional space for clock splitters and extra routing. This ensures that each channel can accommodate clock distribution structures and signal wiring congestion even in the worst-case scenario. This approach simplifies the computation of net crossings because each net in an RSFQ circuit connects only two pins and can be routed over cells. Consequently, there is no need for complex Steiner-tree routing structures as in CMOS hyper-net.

Clock Tree Synthesis and Final Legalization: After placement converges, we use the same RSFQ clock-tree-synthesis method as in qPlace which is based on a modified DME (Deferred-Merge Embedding) algorithm [27]. Clock splitters are then inserted into the placement and legalized using standard techniques [1, 10].

EXPERIMENTS AND RESULTS

Experimental Setup and Implementation

We evaluated qLevelPlace on the ISCAS-85 benchmark with three additional large circuits: a 32-bit ALU (ALU32), a 32-bit multiplier (Multi32), and a 32-bit butterfly unit (BU32). A sample KSA16 GDS layout is shown in Figure 3. Though small by CMOS standards, the ISCAS-85 circuits are already large for current SFQ fabrication, where the RSFQ logic integration density is only $\sim10^4$ gates/$\mathrm{cm}^2$ [24], the arithmetic circuits further stress-test the scalability of our approach. We use qPlace [27] as our baseline for evaluating RSFQ placement quality. Our ablation studies examine linear versus quadratic objectives, level folding, timing-aware edge weighting, and sensitivity to $\lambda$. All methods are evaluated using qPLACE [11] with MIT-LL SFQ5ee technology [29] and the gate library described in [23]. All placement algorithms were prototyped in Python using CPLEX for ILP and standard Python libraries for conjugate-gradient optimization, and were executed on a dual-socket AMD EPYC 7763 server with 128 cores and 2 TB RAM. For level folding, we set ITER_MAX = 3 and $\epsilon= 0.1$. On BU32, the Python prototype takes 24 min, including 4.5 s for ILP and 70 s for QP. Most runtime is spent on Python overhead, including graph copying and traversal.

Performance Comparison

As shown in Table 1, qLevelPlace improves CIL, area, and frequency while generally reducing HPWL. More importantly, it improves the maximum clock frequency by 2.65× on average across the circuits completed by both methods, while producing routable layouts for all evaluated circuits. Moreover, note that qPlace does not yield routable layouts for c7552 and c5315 under its uniform row-spacing algorithm. In contrast, our congestion-aware row spacing (§ 3.4) explicitly reserves inter-row routing resources, which leads to successful routing of all tested designs.

Ckt.	#G	qLevelPlace	qLevelPlace	qLevelPlace	qLevelPlace	qPlace [27]	qPlace [27]	qPlace [27]	qPlace [27]
		Tot. HPWL↓	Tot. CIL↓	Area↓	Freq.↑	Tot. HPWL↓	Tot. CIL↓	Area↓	Freq.↑
c1355	1,052	0.40M	1.6K	6.2M	29.4	1.26M	6.6K	21.5M	12.3
KSA32	1,058	0.41M	1.4K	7.4M	25.0	1.50M	5.5K	15.0M	11.2
c499	1,064	0.44M	1.8K	7.2M	28.0	1.30M	7.5K	24.0M	12.6
c880	1,486	0.73M	1.4K	13.0M	28.5	2.00M	8.0K	26.4M	11.9
c432	1,550	0.79M	1.7K	12.0M	27.0	1.20M	6.6K	30.0M	11.5
c3540	3,672	2.60M	3.9K	30.0M	19.6	3.70M	11.7K	64.0M	7.4
c7552	6,084	5.00M	3.8K	85.0M	18.3	18.0M	22.8K	103M	N/A
c6288	6,245	4.10M	2.8K	57.4M	20.8	5.40M	12.2K	106M	7.1
c5315	8,749	6.70M	4.2K	73.7M	20.0	30.0M	22.4K	149M	N/A
ALU32	13,257	17.3M	5.8K	164M	11.8	22.4M	23.8K	200M	4.0
Multi32	21,204	27.6M	7.9K	240M	9.0	26.9M	26.7K	312M	3.5
BU32	66,962	104.4M	10.6K	837M	6.1	113.5M	56.9K	1,023M	1.6
Avg.	–	1.00	1.00	1.00	1.00	2.31	4.51	2.03	2.65

Ablation Studies

Figure 4a isolates the contribution of the quadratic objective, whereas Figure 4b examines the role of level folding, and Figure 4c analyzes the sensitivity of frequency to $\lambda$. The quadratic objective reduces the estimated CIL by up to 3.06×, as observed on c5315, confirming its effectiveness for RSFQ placement optimization. In fact, the linear model performs worse than the quadratic approach in both estimated CIL and total HPWL, which may seem counterintuitive, as linear objectives typically optimize total wire length. We attribute this to two factors. First, the linear model results in longer wire segments in the X-direction, increasing routing congestion and forcing our congestion-aware Y-axis spacing algorithm to expand the row spacing. On average, this Y-direction expansion accounts for 11.6% of the per-benchmark increase in HPWL. Second, the row-by-row optimization with an approximated L1 objective is more prone to converging to suboptimal local minima.

As shown in Figure 4b, disabling folding increases the layout areas of c3540 and BU32 to 2.51× and 2.34× those of the folded configurations, respectively. For BU32, it also increases total HPWL and CIL by 2.46× and 3.92×, respectively. For smaller benchmarks, the layout area increases to 1.12–2.28× that of the folded configuration, while CIL may increase slightly because folding introduces additional rows and vertical separation. Nevertheless, CIL remains substantially lower than that of qPlace, and the benefits of folding become more pronounced for larger and more congested designs.

We further find the frequency to be insensitive to the anchor weight $\lambda$ (Eq. (6)) within [0, 0.2] (Figure 4c), and adopt $\lambda$=0.1 throughout. Finally, Table 2 evaluates the effect of timing-aware edge weighting. For the critical stages identified from the without-weighting placement, timing-aware weighting reduces the estimated stage delay by 9.3% on average and up to 17.7% for BU32, the largest design, while reducing average CIL by 17% and changing total HPWL only modestly. The method selectively shortens delay-critical connections rather than merely minimizing global wirelength.

Circuit	Tot. HPWL (M)↓	Avg. CIL (k) (Top-10) ↓	Avg. Est. Delay (ps) (Top-10) ↓
c1355	0.41 / 0.40 (0.98)	0.8 / 0.6 (0.80)	27.4 / 25.8 (0.94)
KSA32	0.44 / 0.41 (0.93)	0.7 / 0.7 (0.92)	31.7 / 31.1 (0.98)
c499	0.44 / 0.44 (1.00)	0.8 / 0.7 (0.86)	27.8 / 26.6 (0.96)
c880	0.73 / 0.73 (1.00)	0.9 / 0.7 (0.79)	31.2 / 29.4 (0.94)
c432	0.77 / 0.79 (1.03)	1.1 / 0.9 (0.83)	32.3 / 30.4 (0.94)
c3540	2.50 / 2.60 (1.04)	2.5 / 2.0 (0.82)	47.4 / 42.9 (0.90)
c7552	5.60 / 5.00 (0.89)	3.2 / 2.6 (0.81)	55.2 / 49.0 (0.89)
c6288	4.70 / 4.10 (0.87)	2.3 / 1.9 (0.85)	43.3 / 39.9 (0.92)
c5315	7.83 / 7.60 (0.97)	3.2 / 2.5 (0.77)	49.1 / 41.8 (0.85)
ALU32	17.79 / 17.38 (0.98)	5.4 / 4.4 (0.81)	71.1 / 60.8 (0.86)
Multi32	27.29 / 27.64 (1.01)	7.9 / 6.8 (0.86)	93.4 / 82.1 (0.88)
BU32	103.0 / 104.4 (1.01)	11.2 / 8.9 (0.79)	129.6 / 106.6 (0.82)
Average	– / – (0.97)	– / – (0.83)	– / – (0.91)

Conclusions

Rather than using a uniform CMOS-style cost for all cells, qLevelPlace recognizes that clocked logic gates and unclocked splitters require distinct placement objectives: logic gates lie on independent timing paths and are placed to suppress worst-case interconnect length, whereas splitters act as constrained Steiner-like fanout points and follow the placement of gates. Decoupling the two ruleset placement focus on timing-critical gate-to-gate connections and, with a flexible level-to-row assignment, improves both timing and density.

On the benchmark circuits, qLevelPlace improves clock frequency by 2.65× over qPlace on average, showing that placement benefits substantially from reflecting the timing and fanout characteristics of RSFQ technology. The framework also extends naturally to sequential logic and to co-optimizing clocking, placement, and routing for related gate-level-clocked technologies such as AQFP.